A successive approximation analog to digital converter (SA-ADC) is designed to determine a digital representation of an analog input signal value by means of successive recursion cycles. In each recursion cycle a comparison of the analog input signal with a reference value is used to narrow a range of digital values that contains the digital representation of an analog input signal value. In a conventional SA-ADC the analog signal value is each time compared with the middle value of a current range. Dependent on the result of the comparison, the range is then narrowed to the half of the current range that lies above or below this middle value. This form of narrowing is successively repeated for the ranges that are selected in this way. Analog to digital conversion with such a conventional SA-ADC is quite slow. This is because the comparison with the middle value is implemented with a digital to analog converter (DAC) and a comparator, which need to settle to within half the final quantization step before the next range can be selected.
EP406973 describes a method of improving the speed of an SA-ADC. This method uses overlapping half ranges. Instead of selecting from two half ranges above and below the middle value, a selection from three half ranges of the current range is made. The selection is made from half ranges [0,R/2], [R/4,3R/4], [R/2, R], wherein R is the full size of the current range, and the values in the brackets indicate the upper and lower bounds of the range relative to the lower bound of the range. One of these ranges is selected on the basis of comparisons that indicate that the analog signal values lies with certainty in that range.
The advantage of this method stems from the fact that the comparisons need to be performed with less accuracy than in the conventional method. Less settling time is needed to achieve this accuracy. As a result they can be performed more quickly than in the conventional method. To perform the selection from three ranges the analog signal value is compared with two thresholds, between the middle value and one quarter and three quarters of the current range respectively, for example at ⅜th and ⅝th of the current range. Once the DAC and the comparator have settled to within ⅛th of the current range, one of the half ranges can be selected. This form of narrowing is repeated for the successive ranges that are obtained in this way. The digital representation of the analog signal value is formed by adding results of the comparisons.
However, such an SA-ADC method is still slow. The speed may be improved by performing the comparisons with the two thresholds of each recursion cycle in parallel, but this increases circuit area because it requires two comparators. Moreover, it does not reduce power consumption, which depends mainly on the number of comparisons that have to be performed, be they performed in parallel on different comparators or alternately on the same comparator.